1. Field of the Invention
The invention relates to a method for manufacturing semiconductor devices and, more particularly to, a method for manufacturing semiconductor devices in each of which three kinds of MOS (Metal oxide Semiconductor) transistors having a gate oxide film with different film thicknesses respectively are formed.
The present application claims priority of Japanese Patent Application No. 2000-115695 filed on Apr. 17, 2003, which is hereby incorporated by reference.
2. Description of the Related Art
Most LSIs (Large Scale Integrations), known as a representative of semiconductor devices, are made up of MOS transistors and are excellent for integration density. Such a MOSLSI can utilize its high integration density to reduce costs, thus finding wide applications in a variety of electronic equipment.
In a field of those LSIs, recently, such a type of LSI has been developed called a SOC (System On Chip) that incorporates on its one semiconductor chip a plurality of memories and logics to have desired functions. Since this type of LSI is typically incorporated and used in portable electronic equipment, it is designed to operate on a battery power source and also at the lowest possible source voltage for reducing power consumption.
The logics required in the above-mentioned type of LSI to provide desired functions are made up of a combination of MOS transistors having different properties, specifically of a plurality of kinds of MOS transistors having a gate oxide film with different film thicknesses respectively. The properties of the MOS transistors mainly depend or the film thickness of the gate oxide film in that a thinner the film thickness, a larger becomes an ON-state current, thus enabling high-speed operations. If the gate oxide film is thin, however, a gate leakage current increases, thus running counter to the purpose of power saving. Accordingly, to save power, it is necessary nor to form the gate oxide film too thick.
FIG. 8 schematically illustrates an example of an important portion, of a semiconductor device, that includes a logic circuit made up of three kinds of MOS transistors having different film thicknesses of the gate oxide film. As shown in FIG. 8, this semiconductor device 100 includes a core transistor (high-speed operational transistor) 101 made up of a first kind of MOS transistor M1 (FIG. 7) having a small film thickness for high speed operations of arithmetic/logical operations, image processing, or a like, a sub-core transistor (power saving transistor) 102 consisting of a second kind of MOS transistor M2 (FIG. 7) having a medium film thickness for arithmetic/logical operations, image processing, or a like which do not require such high speed operations as those of the core transistor 101, and a peripheral transistor (low-speed operational transistor 103 consisting of a third kind of MOS transistor M3 (FIG. 7) having a large film thickness which needs not operate at a high speed for driving peripheral circuitry including I/O (input/output) circuits or a like.
Here, terms of small film thickness, medium film thickness, and large film thickness of the gate oxide film do not refer to absolute small, mediums and large values of the gate oxide film thickness respectively but refer to a relative comparison in film thickness of the three kinds of MOS transistors having different gate oxide film thicknesses.
FIG. 7 is schematic cross-sectional view of a specific construction of the semi conductor device 100 as shown in FIG. 8. As shown in FIG. 7, on a same semiconductor substrate 111 of the semiconductor device 100 are formed the first kind of MOS transistor M1 which makes up the core transistor 101 and has a small gate oxide films thickness of 1.5-2.0 nm, the second kind of MOS transistor M2 which makes up the sub-core transistor 102 and has a medium gate oxide film thickness of 2.2-2.5 nm, and the third kind of MOS transistor M3 which makes up the peripheral transistor 103 and has a large gate oxide film thickness of 3.5-7.5 nm.
The first through third kinds of MOS transistors M1 through M3 have source regions 66 through 68, drain regions 7 through 73, three different thicknesses of gate oxide films, a small-thickness gate oxide film 61, a medium-thickness gate oxide film 62, and a large-thickness gate oxide film 52, gate electrodes 63 through 65, and gate side walls 74 through 76 respectively. Each of the source regions 66 through 68 and each of the drain regions 71 through 73 may be either of a so-called xe2x80x9cLDD (Lightly Doped Drain) constructionxe2x80x9d consisting essentially of a high impurity concentration region and a low impurity concentration region or a so-called xe2x80x9cnon-LDD constructionxe2x80x9d consisting essentially of only a high impurity concentration region.
Of these three kinds of MOS transistors M1 through M3, the second kind of MOS transistor M2 making up the sub-core transistor 102 is provided to meet the purpose of power saving with a not so high operation speed as that of the core transistor 101, in such a configuration that its gate oxide film is formed thicker than the first kind of MOS transistor M1 but thinner than the third kind of MOS transistor M3 making up the peripheral transistor 103.
Accordingly, by forming the second kind of MOS transistor M2 to provide the sub-core transistor 102, such an above-mentioned multifarious-functional LSI can be manufactured that can operate at a moderately high speed in arithmetic/logical operations, image processing, and a like with saved power dissipation.
The following will describe a prior art method for manufacturing a semiconductor device along its steps with respect to FIG. 6A through FIG. 6K.
First, as shown in FIG. 6A, for example, a P-type silicon substrate 51 is oxidized to form throughout thereon a first gate oxide film 52a to a thickness of 3-7 nm as an initial gate oxide film. As described later, the first gate oxide film 52a provides the large-thickness gate oxide film 52 of the third kind of MOS transistor M3 making up the peripheral transistor 103. Next, as shown in FIG. 6B, a photo-resist film 53 is applied on a whole surface of the first gate oxide film 52a and then patterned by photolithography to thereby expose only a region 55B, in which the medium-thickness gate oxide film 62 of the second kind of MOS transistor M2 making up the sub-core transistor 102 is to be formed.
Next, as shown in FIG. 6C, residual photo-resist film 53 is used as a mask to selectively implant a fluorine (F) ion through the first gate oxide film 52a into the P-type silicon substrate 51 only in the region 55B, thus forming an ion implantation layer 56.
As described later, this fluorine ion implantation is conducted in order to obtain accelerated oxidation effects when forming by oxidation of the medium-thickness gate oxide film 62 of the second kind of MOS transistor making up the sub-core transistor 102 (FIG. 8) To obtain a sufficient level of the accelerated oxidation effect by use of fluorine, specifically, fluorine ions are implanted under such preset ion implantation conditions that the fluorine may have a range Rp measuring about 10 nm or less in the P-type silicon substrate 51, in order to deposit much of the fluorine on the upper surface of the P-type silicon substrate 51 in the region 55B.
The present applicant applied earlier a method for using argon (Ar) as an ion implantation impurity to obtain the accelerated oxidation effect in forming the medium-thickness gate oxide film (Japanese Patent Application No. Hei 12-32047, filed Feb. 9, 2000, unpublished at present). Later, however, the present applicant found that use of argon as an impurity damages the P-type silicon substrate 51 when ions are implanted, thus increasing a gate leakage current, to guard against which the present applicant found that use of fluorine in place of argon can solve such a disadvantage. Accordingly, as mentioned above, use of fluorine as the ion implantation impurity is effective in obtaining the accelerated oxidation effect.
Next, as shown in FIG. 6D, the photo-resist film 53 (FIG. 6C) contaminated by ion implantation is removed and then a new photo-resist film 54 is applied and patterned to expose the above-mentioned region 55B and a region 55A, in which the small-thickness gate oxide film 61 of the first kind of MOS transistor M1 (FIG. 7) making up the core transistor 101 (FIG. 8) is to be formed. Next, as shown in FIG. 6E, a residual of the photo-resist film 54 is used as a mask to remove the first gate oxide film 52a in the regions 55A and 55B.
Next, as shown in FIG. 6F, the photo-resist film 54 is removed. Specifically, this photo-resist film 54 is removed in two steps of a plasma removal step and an acid removal step. First, by a first step of plasma removal, most of the photo-resist film 54 is removed. By this first step alone, however, the photoresist film 54 cannot completely be removed, so that by a second step of acid removal by use of a mixed solution of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2), the residual of photo-resist film 54 is completely removed. During this acid removal step, a chemical oxide film 57 is formed on the upper surface of the P-type silicon substrate 51 to a film thickness of 0.8-1.0 nm.
This film thickness of the chemical oxide film 57 is not negligible as compared to the above-mentioned small-thickness gate oxide film, 61, so that if that chemical oxide film 57 is left as it is, that small-thickness gate oxide film 61 may not be controlled easily. To guard against this, the chemical oxide film 57 needs to be removed.
Next, as shown in FIG. 6G, the P-type silicon substrate 51 is cleaned by washing it using a mixed solution of sulfuric acid and hydrogen peroxide. On the surface of the P-type silicon substrate 51, however, the chemical oxide film 57 is formed again. Therefore, as shown in FIG. 6H, the chemical oxide film 57 is washed and removed with a diluted hydrofluoric acid.
Next, as shown in FIG. 6I, oxidation processing is conducted to simultaneously form the small-thickness gate oxide film 61 with a thickness of 1.5-2.0 nm in the region 55A on the P-type silicon substrate 51 and the medium-thickness gate oxide film 62 with a thickness of 2.0-2.5 nm in the region 55B on the P-type silicon substrate 51. Second gate oxide films provide the small-thickness gate oxide film 61 and the medium-thickness gate oxide film 62, as the above-mentioned first gate oxide film 52a provides the large-thickness gate oxide film 52. During this oxidation processing, on the upper surface of the region 55B into which fluorine ions have been implanted beforehand, the medium-thickness gate oxide film 62 thicker than the small-thickness gate oxide film 61 formed on the region 55A is grown by the accelerated oxidation effect. At the same time, by this oxidation processing, the first gate oxide film 52a, which is the initial gate oxide film, is increased in film thickness to some extent, thus forming the large-thickness gate oxide film 52 with a thickness of 3.5-7.5 nm on the upper surface of a region 55C, in which the third kind of MOS transistor making up the peripheral transistor 103 (FIG. 8) is to be formed.
Next, as shown in FIG. 6J, throughout on the small-thickness gate oxide film 61, the medium-thickness gate oxide film 62, and the large-thickness gate oxide film 52 is formed a poly-crystal silicon film by CVD (Chemical Vapor Deposition) or a like, all of which are then patterned to form the gate electrodes 63 through 65 in the regions 55A through 55A respectively. Next, as shown in FIG. 6K, ions of an N-type impurity are implanted in a self-alignment manner by use of those gate electrodes 63 through 65 to form respective source regions 66 through 68 and the respective drain regions 71 through 73 and then to form, by a known method, side wall films 74 through 76, source electrodes (wiring lines) 77 through 79, and drain electrodes (wiring lines) 81 through 83 are formed to thus complete the semiconductor device 100 such as shown in FIG. 7.
The prior art semiconductor device manufacturing method, however, suffers from a problem of reduction in the accelerated oxidation effect due to fluorine ion implantation.
That is, as described with FIG. 6C, to obtain a sufficient level of the accelerated oxidation effect, conventionally fluorine ions have been implanted under such conditions that the range Rp may be about 10 nm or less in the P-type silicon substrate 51 in order to deposit much of the fluorine in the region 55B on the upper surface of the P-type silicon substrate 51. If, however, fluorine ions are implanted in such a manner that its range Rp may be set at such a comparatively shallow position in the P-type silicon substrate 51, the ion implantation layer 56 is formed near the surface of the P-type silicon substrate 51, so that the fluorine, which will be diffused rapidly in, the silicon substrate and readily evaporated, would be evaporated readily from the ion implantation layer 56 off the substrate 51 by the effect of a high temperature during the subsequent oxidation processing. This in turn reduces concentration of fluorine in the region 55B, in which the medium-thickness gate oxide film, gate oxide film 62, is to be formed.
Also, the prior art semiconductor device manufacturing method suffers from a problem in that when the gate oxide films, the small-thickness gate oxide film 61, the medium-thickness gate oxide film 62, and the large-thickness gate oxide film. 52 are formed by oxidation processing after fluorine ions are implanted, in particular, the medium-thickness gate oxide film 62 is deteriorated, thus increasing its gate leakage current.
That is, when typically ions of a desired impurity are implanted into the P-type silicon substrate 51, defects due to this ion implantation occur inevitably inside the P-type silicon substrate 51, especially around the range Rp as a center numerously. This holds true also with the case of implantation of a fluorine ion. Such defects generated inside the P-type silicon substrate 51 by the fluorine ion implantation are readily caused to the medium-thickness gate oxide film 62 by the effect of a high temperature during the subsequent oxidation processing, thus deteriorating the medium-thickness gate oxide film 62. This in turn further increases the gate leakage current of the semiconductor device 100.
Further, as described with FIG. 6H, the first gate oxide film 52a formed already in the region 55C, providing the large-thickness gate oxide film 52, is etched and deteriorated when the chemical oxide film 57 is washed and removed with DHF. This would farther increase the gate leakage current of the relevant semiconductor device.
In view of the above, it is an object of the invention to provide a method for manufacturing a semiconductor device wherein when three kinds of MOS transistors having a gate oxide film with a small film thickness, a medium film thickness, and a large film thickness respectively are formed on the same semiconductor substrate, gate oxide films can be prevented from being deteriorated while maintaining a high level of an accelerated oxidation effect of a medium-thickness gate oxide film, thus reducing a gate leakage current.
According to a first aspect of the present invention, there is provided a semiconductor device manufacturing method for forming three kinds of MOS transistors having a gate oxide film with a small film thickness, a medium film thickness, and a large film thickness respectively on a semiconductor substrate, including:
an initial gate oxide film forming step for forming an initial gate oxide film with the large film thickness throughout on the semiconductor substrate;
an initial gate oxide film removing step for selectively removing a region of the initial gate oxide film on the semiconductor substrate in which region the gate oxide film with the small film thickness and the gate oxide film with the medium film thickness are to be formed;
a fluorine ion implanting step for selectively implanting ions of fluorine only in a region on the semiconductor substrate in which region the gate oxide film with the medium film thickness is to be formed; and
an oxidation processing step for simultaneously forming in a region on the semiconductor substrate in which region the gate oxide film with the small film thickness is to be formed and in a region on the semiconductor substrate in which region the gate oxide film with the medium film thickness is to be formed a gate oxide film with a small film thickness and a gate oxide film with a medium film thickness which are both smaller than a film thickness of the initial gate oxide film, respectively.
According to a second aspect of the present, there is provided a semiconductor device manufacturing method for forming three kinds of MOS transistors having a gate oxide film with a small film thickness, a medium film thickness, and a large film thickness respectively on a semiconductor substrate, including:
a first gate oxide film forming step for forming a first gate oxide film having the large film thickness throughout on the semiconductor substrate;
a first gate oxide film removing step for selectively removing a region of the first gate oxide film on the semiconductor substrate in which region the gate oxide film with the small film thickness and the gate oxide film with the medium film thickness are to be formed;
a fluorine ion implanting step for selectively implanting ions of fluorine only in a region on the semiconductor substrate in which region the gate oxide film with the medium film thickness is to be formed; and
a second gale oxide film forming step for forming in a region on the semiconductor substrate in which region the gate oxide film with the small film thickness is to be formed and in a region on the semiconductor substrate in which region the gate oxide film with the medium film thickness is to bee formed a second gate oxide film including a gate oxide film with a small film thickness and a gate oxide film with a medium film thickness which are both smaller than a film thickness of the first gate oxide film, respectively.
According to a third aspect of the present invention, there is provided a semiconductor device manufacturing method for forming three kinds of MOS transistors having a gate oxide film with a small film thickness, a medium film thickness, and a large film thickness respectively on a semiconductor substrate, including:
a first gate oxide film forming step for forming a first gate oxide film having the large film thickness throughout on the semiconductor substrate;
a first gate oxide film removing step for selectively removing a region of the first gate oxide film on the semiconductor substrate in which region the gate oxide film with the small film thickness and the gate oxide film with the medium film thickness are to be formed;
a chemical oxide film forming step for forming a chemical oxide film in a region on the semiconductor substrate in which region the gate oxide film with the small film, thickness and the gate oxide film with the medium film thickness are to be formed;
a fluorine ion implanting step for selectively implanting ions of fluorine through the chemical oxide film only in a region on the semiconductor substrate in which region the gate oxide film with the medium film thickness is to be formed; and
a second gate oxide film forming step for, after the chemical oxide film is removed, forming in a region or the semiconductor substrate in which region the gate oxide film with the small film thickness is to be formed and in a region on the semiconductor substrate in which region the gate oxide film with the medium film thickness is to be formed a second gate oxide film including a gate oxide film with a small film thickness and a gate oxide film with a medium film thickness which are both smaller than a film thickness or the first gate oxide film, respectively.
In the foregoing third aspect, a preferable mode is one wherein in the fluorine ion implanting step, fluorine ions are implanted under such preset conditions that a range Rp of the fluorine may measure 15-150 nm in the semiconductor substrate.
Also, according to a fourth aspect of the present invention, there is provided a semiconductor device manufacturing method for forming three kinds of MOS transistors having a gate oxide film with a small film thickness, a medium film thickness, and a large film thickness respectively on a semiconductor substrate, including:
a first gate oxide film forming step for forming a first gate oxide film having the large film thickness throughout on the semiconductor substrate;
a first gate oxide film removing step for selectively removing a region of the first gate oxide film on the semiconductor substrate in which region the gate oxide film with the small film thickness and the gate oxide film with the medium thickness are to be formed;
a chemical oxide film forming step for forming a chemical oxide film in a region on the semiconductor substrate in which region the gate oxide film with the small film thickness and the gate oxide film with the medium film thickness are to be formed;
a fluorine ion implanting step for selectively implanting ions of fluorine through the chemical oxide film only in a region on the semiconductor substrate in which region the gate oxide film with the medium film thickness is to be formed; and
a second gate oxide film forming step for, with the chemical oxide film left unremoved, forming in a region on the semiconductor substrate in which region the gate oxide film with the small film thickness is to be formed and in a region on the semiconductor substrate in which region the gate oxide film with the medium film thickness is to be formed a second gate oxide film including a gate oxide film with a small film thickness and a gate oxide film with a medium film thickness which are both smaller than a film thickness of the first gate oxide film, respectively.
In the foregoing fourth aspect, a preferable mode is one wherein in the fluorine ion implanting step, fluorine ions are implanted under such preset conditions that a range Rp of the fluorine may measure about 20 nm in the semiconductor substrate. Also, a preferable mode is one wherein the fluorine ion implanting step is replaced by an alternative fluorine ion implanting step for implanting a fluorine ion not through the chemical oxide film but directly into the semiconductor substrate.
With the above configurations, fluorine ions are implanted in a region, in which the medium-thickness gate oxide film is to be formed, under such ion implantation conditions that the range of fluorine Rp may measure 15-150 nm in the substrate, to subsequently remove the chemical oxide film on the surface of that region and then form by oxidation processing the medium-thickness gate oxide film in that region, thus enabling, during the oxidation processing, suppressing fluorine evaporation and also preventing defects from being caused to the medium-thickness gate oxide film when fluorine ions are implanted.
Also, fluorine ions are implanted in a region in which the medium-thickness gate oxide film is to be formed under such ion implantation conditions that the range of fluorine Rp may measure about 20 nm in the substrate, to subsequently oxidize that region as covered with the chemical oxide film in order to form the medium-thickness gate oxide film in that region, thus enabling, during the oxidation processing, suppressing fluorine evaporation and also preventing defects from being caused to the medium-thickness gate oxide film when fluorine ions are implanted.
Thus, when forming the three kinds of MOS transistors having small-thickness, medium-thickness, and large-thickness gate oxide films on the same semiconductor substrate, it is possible to prevent the gate oxide films from being deteriorated, thus capable of reducing gate leakage current, while maintaining the accelerated oxidation effect of the medium-thickness gate oxide film at an enhanced level.